In semicustom and custom VLSI designs, the designer is usually constrained by real estate utilization as a result of yield, which directly affects cost, and performance tradeoffs. By real estate is meant the extremely limited amount of room on a typical integrated circuit chip. In memory circuits and a lot of digital logic circuits it is desirable to have as much memory on a chip as possible, but, on the other hand, either the area that the cell occupies is too large due to limitations in the technology, as in a single polycrystalline silicon (polysilicon) process, or the circuit yield is lowered when double level polysilicon is used. The capability of fabricating a high resistive load on a chip is very important in putting any cross latched designs such as static random access memories (SRAMs), etc., on a chip because it can reduce the cell area. (A cross latched design refers to a circuit configuration that is used in a regenerative circuit. All static memory needs a regenerative circuit to retain a bistable state in digital memory.) It is preferrable to use a single polysilicon process due to yield concerns; however, for high performance VLSI chips, the polysilicon is usually replaced by polycide, which is a sandwiched layer of silicide and polysilicon with lower resistivity to improve performance. To date, there are no documented ways of fabricating high resistive polysilicon loads simultaneously in a single level polycide gate technology. Some prior art uncovered in this field is discussed below.
U.S. Pat. No. 4,640,844 to Neppl et al discloses a method of forming gate electrodes in a polycide layer. A polycide layer is produced by deposition of an undoped polycrystalline silicon layer on an n+ doped silicon substrate, followed by deposition of a tantalum disilicate layer on top of the polysilicon. Structuring of the gates is then accomplished by reactive ion etching. P channel source and drain zones are produced by boron ion implantation while a photoresist covers the zones of the n channel transistors. A second photoresist covers the zones of the p channel transistors while n channel source and drain zones are produced by arsenic ion implantation.
U.S. Pat. No. 4,406,051 to Iizuka discloses a method of manufacturing a semiconductor device in which a high resistivity element is formed by controlled doping of a polycrystalline silicon layer. A polycrystalline silicon layer is grown over a semiconductor substrate and patterned to cover a previously formed contact hole. A heavy doping of oxygen or nitrogen by ion implantation forms the resistive region.
U.S. Pat. No. 4,451,328 to Dubois discloses a process for forming high resistance elements in IC structures. A layer of polycrystalline silicon is deposited on an oxide insulated semiconductor substrate. Resistance is obtained in desired areas by diffusion or ion implantation. Resin plugs are placed in the resistive areas and conductive regions are created by further doping of unprotected areas. Finally, a metal silicide layer is deposited and the resin is etched to reveal the resistive elements.
According to the present invention, RIE (reactive ion etching) with appropriate end point detection plus a common doping technique is used to fabricate a high resistive load on a single level polycide in a typical NMOS/CMOS process. While in the SALICIDE (Self Aligned Silicide) CMOS process case, a new process is proposed to fabricate a high resistive load on a single level polycide process. By etching away a top silicide layer which exposes an underlying polysilicon layer and then implanting with a heavy dose of boron, the high resistive load on the integrated circuit is formed. Very often the highly resistive polysilicon is implemented as a second polysilicon layer, which increases the process complexity vastly. This invention proposes the use of only one polycide layer to implement both the low resistive gate and interconnect the high resistive polysilicon needed to implement certain circuit functions.